1. Field of the Invention
The present invention relates to semiconductor memories, and more particularly to the writing of a constant value to a plurality of addresses simultaneously. Still more particularly, the present invention relates to the fast writing of a constant value to a plurality of column-wise contiguous cells of the memory.
2. Background and Related Art
Computer graphics display systems, e.g., scientific workstations, are widely used to generate two-dimensional (2D) representations of three-dimensional (3D) data for scientific, engineering, manufacturing, and other applications. The image displayed on the screen is stored in a memory called the frame buffer. The frame buffer is usually comprised of both Dynamic Random Access Memory (DRAM) and Video Random Access Memory (VRAM), as is known to those skilled in the art. The rate at which new data may be written to the frame buffer determines the system's performance.
However, the performance perceived by the user is based on other factors in addition to the rate at which new image data is written to the frame buffer. For example, the amount of time spent refreshing the dynamic memory devices and scanning the image to the screen adds to the perceived amount of time required to render new data. Additionally, prior to drawing a new frame, the data in the frame buffer must be erased to provide a "clean" drawing area. The amount of time required to clear the portion of the frame buffer associated with the current application's window also adds to the total perceived time for rendering an image.
Many graphics adapters are "single buffered," meaning that there is only one bank of VRAM associated with the image on the screen. As a result, the user often sees the old image being cleared and the new image being generated because the buffer being altered and the buffer being scanned to the monitor are the same entity. Consequently, in a single-buffered system, time spent clearing the buffer greatly detracts from the front-of-screen image quality. The image quality is generally resolved by double-buffering the frame buffer; where one buffer (the update buffer) is used to generate the next image, while a second buffer (the display buffer) is displayed. Once rendering to the update buffer is complete, the buffers are swapped (usually during the monitor's vertical retrace period--the time spent waiting for the electron beam to be repositioned to the top of the screen for the next refresh). The data in the new update buffer is then erased, and the next image is rendered. In the case of a double-buffered system, the time required to clear the old image simply adds to the overall perceived rendering time.
Clearing operations are not only used to initialize the frame buffer prior to generating the screen (i.e., once per frame). Some graphics primitives require multiple passes through the hardware and the use of auxiliary bit planes in the frame buffer to tag certain pixels. Either before or after such a primitive is rendered, the auxiliary planes must be initialized. The time spent initializing the auxiliary planes also adds to the perceived rendering time of an image.
In U.S. Pat. No. 4,961,171 Pinkham and Balistreri describe a memory in which there exists an on-chip data register that may be used during ensuing write operations. On standard VRAM devices, this register is commonly known as the "color register." The use of this register is further described by Pinkham and Balistreri in U.S. Pat. No. 4,807,189, wherein they describe a means of writing the data in the color register to multiple adjacent cells. This function has been adopted in the VRAM industry as "block write." Yet another function using the color register is defined by Kamisaki in U.S. Pat. No. 5,003,510 wherein he discloses writing the value in the color register to all cells in a given memory row. This function is known to those skilled in the art as "flash write." U.S. Pat. Nos. 4,961,171; 4,807,189; and 5,003,510 are incorporated herein by reference.
In single-window (or non-windowed) systems, such as the IBM 5086 Model 2, flash write is particularly valuable in that it allows the screen to be cleared rapidly. Assuming that all 512 rows of the VRAM are cleared and that each flash write consumes 160 nanoseconds (ns), it requires only 82 microseconds (.mu.s) to clear the entire frame buffer (window). The advent of windowed environments, such as those supported on the IBM RISC System/6000.RTM. (RISC System/6000 is a registered trademark of IBM Corporation), has reduced the utility of flash write because windows may occupy any sub-region of the screen, and do not map to a whole number of rows in memory. In the most time-consuming case, pixel locations within a window must be cleared (set to a constant) one at a time. Relative to flash write, this represents a 512-fold decrease in performance (there are 512 columns in a row of a standard VRAM). Block write partially addresses this issue. Block write allows a plurality of cells within a group, or "block", of cells with common most-significant bits of their address (i.e., a group of adjacent cells aligned to a given power of 2) to be written simultaneously. The most common mode of block write allows any or all of 4 contiguous column addresses to be written simultaneously as masked by 4 bits of the data bus. Some memory devices now offer 8-column block write, i.e., data may be written to any subset of the 8 columns within the selected block based on 8 bits of the data bus. Thus, there is a 128-fold (64-fold in 8-column block write parts) depreciation in the pixel-per-second clearing performance of windowed systems using block write versus flash write. As an example, it requires 648 .mu.s to clear a 900.times.720 window (a common window size). This assumes 40 nanoseconds (ns) per block write cycle, 8-column block write, and a 5-way memory interleave as is common in many workstations. (Five 8-column block write VRAMs can render 40 pixels every 40 ns, or 1 pixel per nanosecond, and there are 648,000 pixels in a 900.times.720 window.) Further increases in bandwidth past 8-column block write is not likely because of the pins required to control the column selects would out-grow the width of the data bus.